Master To Do List for PulseNet:

1. SETI_IO
   1. Precisely document the problems from rev1
   2. Recode seti_io.v
   3. Check functionality
   4. Have others check seti_io.v for problems
   5. Convert to layout using Snake
   6. Verify using Nanosim
2. Astronomy
   1. Precisely document the problems (if any) from rev1
   2. Recode astronomy.v
   3. Check functionality
   4. Have others check astronomy.v for problems
   5. Convert to layout using Snake
   6. Verify using Nanosim
3. Clock tree
   1. Construct good RC spice model of long wires
   2. Simulate clock tree in Nanosim
   3. Verify that all other long signal/control lines on chip have adequate drivers.
4. ESD protection
   1. Lay out new ESD pads (started)
   2. Test in Nanosim (?)
5. Develop interface between verilog and Nanosim
   1. Get verilog to output vector files.
   2. Get Nanosim to automatically check that its simulation matches the verilog output.
6. Simulation interface/testbed
   1. Set up a general Nanosim testbed.
   2. Should be for the whole chip portions of PulseNet should be turned off by grounding the appropriate pins.
   3. Allow for programming of internal control lines when blocks turned off.
7. Nanosim testing of components from rev1 that were only tested in IRSIM
   1. Clock distribution network
   2. Memory controller
   3. Pay particular attention to timing
8. Full-chip simulation
   1. Gradually build up a full-chip simulation, starting with the simulation interface/testbed, and adding the following components:
      1. Clock tree
      2. One sampler block
      3. All sampler blocks
      4. Memory block
      5. SETI IO
      6. Astronomy
   2. Issues to think about:
      1. Timing is critical; look for race conditions
      2. Know when when to use schematic/layout netlists. For clock tree, the layout netlist is a must. For most others, start with the schematic layout, and run it again with the layout netlist if there's time.
      3. Use Vdd1, Vdd2, etc. to turn on/off various domains.
9. Tape-out checks
   1. DRC (Design Rule Check in Magic)
   2. LVS (Layout vs. Schematic)
   3. Check for metal-fill rules compliance
   4. Routing through wells.
   5. Check for floating wells.
   6. Routing through labels.
   7. Fanout check? Possibly write script to compute fanout ratio for each node (sum C_out)/(sum C_in)
10. Design Review
    1. Tape-out is December 5th! Be ready!
    2. Stay current with these web pages; use them for the review.
    3. Basic material to include:
       1. Description of blocks
       2. Simulation runs: what they verified, how the simulations were run, my confidence from these simulations
       3. Master checklist.
       4. Layout? See this page for an example
11. Ship it!
    1. Check all issues raised in the design review.
    2. Double check all items above. Make sure that all loose ends are tied up.
    3. Redo Tape-out checks.