7 PulseNet Design Review

PulseNet Design Review:

  1. Preamble
    1. Goals for design review
    2. PulseNet basics
    3. Rev1: Problems and lessons learned -- ALMOST DONE
    4. Issues raised in Design Review
  2. All-sky optical SETI and PulseNet
    1. The experiment
    2. Boards, chips, data flow
    3. Package and socket
  3. Interface at the board level
    1. Pinout
    2. Analog samplers
    3. Astronomy and SETI interfaces with microcontrollers
    4. Clock
    5. Ring oscillator
    6. Voltage references
    7. Power and ground
  4. Intra-chip communication and function
    1. Block diagram
    2. Block descriptions
      1. sampencbank
      2. SETI_IO
      3. membank
      4. astronomy
      5. clocktree
      6. ringosc
    3. Data flow
  5. Circuit details
    1. Clocking scheme
    2. Samplers
    3. Memory
    4. SETI_IO
    5. Astronomy -- NEEDS WORK
    6. Important on-chip signals -- NEEDS WORK
  6. Layout details
    1. Overall layout -- NEEDS WORK
    2. Vdd and Gnd
    3. Voltage references
    4. Clock routing
    5. Global signal routing -- NEEDS WORK
    6. Analog signals
  7. Simulations
    1. Simulation procedures -- NEEDS WORK
    2. SETI_IO module
    3. Astronomy module -- NEEDS WORK
    4. Sampler bank -- NEEDS WORK
    5. Muxes
    6. Memory -- PARTIAL
    7. Clocks
    8. Pads -- SIMULATION NOT DONE
    9. Power dissipation
    10. Ground bounce -- NEEDS WORK
    11. Full chip -- SIMULATION NOT DONE
  8. Tape-out checks
    1. DRC (Design Rule Check in Magic)
    2. LVS (Layout vs. Schematic)
    3. Metal-fill rules compliance
    4. Routing through wells -- NEEDS WORK
    5. Floating wells -- NEEDS WORK
    6. Routing through labels
    7. Fanout check -- NEEDS WORK
  9. Other issues
    1. Naming conventions
    2. Tools used
      1. Commerical tools
      2. Scripts written
    3. Testing real chips

Andrew Howard
Last updated: 3/9/2005
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